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NPU(Neural Processing Unit), AI Acclerator 관련 논문 정리 [2] architecture 본문
NPU(Neural Processing Unit), AI Acclerator 관련 논문 정리 [2] architecture
자전거 타는 구구 2020. 7. 10. 17:05[2] architecture
Chen, Yu-Hsin, Joel Emer, and Vivienne Sze. "Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks." ACM SIGARCH Computer Architecture News 44.3 (2016): 367-379.
Moons, Bert, and Marian Verhelst. "A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets." 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). IEEE, 2016.
Albericio, Jorge, et al. "Cnvlutin: Ineffectual-neuron-free deep neural network computing." ACM SIGARCH Computer Architecture News 44.3 (2016): 1-13.
Reagen, Brandon, et al. "Minerva: Enabling low-power, highly-accurate deep neural network accelerators." 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2016.
Whatmough, Paul N., et al. "Dnn engine: A 28-nm timing-error tolerant sparse deep neural network processor for iot applications." IEEE Journal of Solid-State Circuits 53.9 (2018): 2722-2731.
Han, Song, et al. "EIE: efficient inference engine on compressed deep neural network." ACM SIGARCH Computer Architecture News 44.3 (2016): 243-254.
Liu, Daofu, et al. "Pudiannao: A polyvalent machine learning accelerator." ACM SIGARCH Computer Architecture News 43.1 (2015): 369-381.
Liu, Shaoli, et al. "Cambricon: An instruction set architecture for neural networks." 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2016.
Jouppi, Norman P., et al. "In-datacenter performance analysis of a tensor processing unit." Proceedings of the 44th Annual International Symposium on Computer Architecture. 2017.
Caulfield, Adrian M., et al. "A cloud-scale acceleration architecture." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016.
Sharma, Hardik, et al. "From high-level deep neural models to FPGAs." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016.
Mahajan, Divya, et al. "Tabla: A unified template-based framework for accelerating statistical machine learning." 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2016.
Pham, Phi-Hung, et al. "NeuFlow: Dataflow vision processing system-on-a-chip." 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012.
Alwani, Manoj, et al. "Fused-layer CNN accelerators." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016.
Rhu, Minsoo, et al. "vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016.
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